Showing posts with label layout. Show all posts
Showing posts with label layout. Show all posts

Monday, August 30, 2010

Pick and Place Outputs Options


I have problem about generating Pick and Place file. The value of Center-Y is bigger than the board Y size, how can I fix this problem?
After spent some hot surfing, found http://wiki.altium.com/display/ADOH/Preparing+the+Board+for+Design+Transfer said Moving the Board Shape which I think that I successfully moved the board into origin point then go for generating pick and place file.

From Design > Board Option to check current sheet position. My sheet position is X: 25.4mm, Y:25.4mm, Width: 254mm, Height: 203.2mm.

Then follow instructions above to use Move Board Shape to move shape to oringin (0, 0). Select Edit » Move » Move Selection by X, Y, then enter X: -25.4mm, Y:-25.4mm.

Friday, February 26, 2010

Layout Guide Criteria

These days I am reviewing layout guides for keys parts about Spartan-6 FPGA Layout H/W platform, so the layout criteria about this projects can be listed up together. This phase is important that a real placement & route during layout house processing. Pheu, really learned a lot! jeje...

Wednesday, February 24, 2010

廣邀 KiCad 愛好者


相信你收尋到這裡, 想必也是受 KiCad 的 Open Source Layout Tool 給吸引過來!!! 我們是一群堅信與邁向開發 Open Source Hardware Plate form 的 Copyleft 公司 sharism.cc, 歡迎任何想以 KiCad 來開發 Open Source Hardware 產品的朋友, 加入這個共同 layout 開發的環境.目前主要的 Project 項目有:

1, Projects List , 以北京君正 Ingenic jz47xx 32位嵌入式处理器,基于君正创新的XBurst CPU微体系架构系列硬體開發為主軸之移動多媒体產品.

2,上述 Projects lists 裡之所有基於開放原始碼延伸之各類軟體開發.

歡迎有興趣的朋友, 可加入 Development List 討論與學習, 或閱接收最新消息.

Wednesday, January 27, 2010

Comparisons on special module implemented between KiCad and others layout tool


These days I am little bit pissing myself off to learn KiCad that loving it but hardly to me on linux side. In order to overcome my poor linux skill, i must use my linux laptop everyday. Not only basic also electronic engineering requirements. We are using a two circle rings as button function in KiCad, but there still have some problems. I'd like to fix it but i cant at this moment from ability. So only need spend more time on KiCad field. The followings are just posted on Qi wiki first.
  • Comparisons between RC1 and RC2
S50 key btn on RC1 board

avt2 RC1 S50 key
The following pictures are gerbers in different stacking layers
  • Problem 1
The rc2 mask and solder layer are not circle as same as rc1, if this is the KiCad's limit, then we need to think other way to solve this. Since the metal domn must not contact with copper well when user push buttons due to contact area is too small.
  • Problem 2
The copper layer (GND) is connected to S50's outside ring (short condition).
The above is the problems now I meet, hope they can be fixed later.

Monday, January 25, 2010

How to install & build KiCad 2009-02-16 on Ubuntu 9.10


Ubuntu 9.10 (Karmic Koala)

  • sudo apt-get install build-essential cmake doxygen subversion libglut3 libglut3-dev zlib1g zlib1g-dev libboost-dev libwxbase2.8-0 libwxbase2.8-dev libwxgtk2.8-dev
  • wget http://iut-tice.ujf-grenoble.fr/cao/kicad-sources-2009-02-16.tar.gz
  • tar zxvf kicad-sources-2009-02-16.tar.gz
  • cd kicad-2009-02-16
  • mkdir build
  • cd build
  • cmake ..
  • make -j16
  • sudo make install
now you can type 'kicad' in your terminal, also [applications] -> [programming] in gnome panel. to remove the kicad you can run "sudo make uninstall" under the build folder

Links


Before doing install, remember to uninstall previous KiCad version firstly.

sudo apt-get remove kicad

This is posted that I wanted to upgrade my linux 9.04 to 9.10. Then install new version of KiCad 2009-02-16 version. And Xiangfu he knows more Linux knowledge than me, so I asked him to help me that how i can do this. Thanks for Xiangfu's post.

Monday, January 4, 2010

[Kicad] DRC err and Drill file


Today I tried to know that how to create a drill file in PCBnew of Kicad and check pcb by DRC function. Then something encountered I didn't know. So I posted email to list to ask. We'll see the real answers later. jeje...


Thursday, December 31, 2009

Some Layout Notes in avt2 RC2 20091230


I just uploaded layout notes on http://wiki.qi-hardware.com/wiki/Layout_notes_avt2_RC2_20091230
They are under http://wiki.qi-hardware.com/wiki/AVT2_RC2_Reference_Board#LAYOUT_NOTES, There are the layout histories about Qi's reference design board. We are the open team for everything on h/w platform. If you are interested with this open linux-based platform about consumer products, for example portable game player, mp3 player, dictionary, nano notebook or even like a high platform which can control Arduino board. Then you can use Qi's Ben NanoNote or its reference design board to reach variable applications. Check it if you want to follow hardware development, feedback welcome.

Monday, December 7, 2009

How to Playcement and Layout Bypass Capacitor Sequencing with Vils


Bypass Capacitor is used to bypass the power supply or other high impedance component of a circuit. I found that any through vils applied in board design, you must to know what the signal you want to let it pass through and what signals you want to eliminate as more as possible. For example, there's a capacitor needed placement as close as LCD FPC connector with 10uF/10V. but how you route the trace on board?
 The above placements of vils are not perfect. You can see the descriptions of bypass capacitor first.Then you can check Parasitic Inductance of Bypass Capacitor II to know what's relationship between your vils with your bypass capacitor? and how's the parasitic inductance of bypass capacitor?

Putting aside the very basics of the theory, let us use the simplest principles of the road point of view, in the end the diameter of vil how we choose? First of all, if one has a four-lane highway through the lane, and then an A at suddenly reduced to two lanes of carriageway; but through the B Division turned back after the four-lane carriageway, what will it happen? A result, will be have traffic jam phenomenon before entering the A, but once through A then becomes smooth into two lanes. After a B point, the phenomenon of traffic congestion would not occur again. 

Back to the original topic, if the bypass capacitor connected to vil which its circumference range as long as alike AB, and then also if the original trace width and following trace width is inconsistent, there will be unintended consequences.
 
If track width is 0.0118", then the both terminal side of each wire trace, the vils should bigger than track width;
for example:
        track width = 0.0315", 
        through vil's diameter = 0.0118"
        then the length of the circumference (c) = 2 * 3.141592 * ( 0.0118 / 2 ) = 0.037"
since we are not sure normally the quality on processing vils on pcb maker, so the most safe way is to put
2 pcs of 0.0118" through vil (total equivalent width = 0.037 * 2 = 0.074) on the two ends of trace.

From above illustration, you can see either 2πis shorter than layer 1 trace width or layer 2 trace width, you will have a wrong choose on vil width type or amount of vils.

Let's go back a little bit of theory side, please reference to this in advance. Through it, in general, if you want to have an overall quick view, you can watch its Index by Keyword for your like hand book.

To be continued.
Ref. : PCB LAYOUT AUTHORITY

Thursday, December 3, 2009

Qi Hardware Inc. has Kicad version reference design

Qi Hardware Inc. just finished pcb and gerber files used by Kicad free tool, i am double checking these great results. You can see here to know all of them.